Sub-5 nm FIB direct patterning of nanodevices

Nanoengraving of membranes as a template for nanopores fabrication is an application field of growing interest. Similarly to the formation of ion tracks in membranes created when high-energetic ions pass trough thin foils, it is possible with a FIB system to fabricate, design and organise nanodevices within thin membranes. In this work, we detail the advanced methodology we have carefully optimised for such deep sub-10 nm nanodevices fabrication using our high-performance FIB instrument.     

Growth of SiGe film by using a single-wafer rapid thermal processing UHV/CVD system

Ultra-high-vacuum chemical vapor deposition (UHV/CVD) system displays excellent performance for the growth of high-quality SiGe film. Investigations have shown that have shown that SiGe film grown by this system has high quality. A 10-finger SiGe hetero-junction bipolar transistor (HBT) device displayed good electrical performance. The current gain was about 500, and the f_T was 5.4 GHz with f_max 7.5 GHz under V_CB=3 V, I_C=10 mA. This article is based on a presentation in “The 7th Korea-China Workshop on Advanced Materials” organized by the Korea-China Advanced Materials Cooperation Center and the China-Korea Advanced Materials Cooperation Center, held at Ramada Plaza Jeju Hotel, Jeju Island, Korea on August 24–27, 2003.     

基于介质上电润湿的液滴产生器的研究

根据介质上电润湿的基本原理,对用于数字微流控系统的"三明治"结构器件中影响液滴输运和产生的因素进行了理论分析,并研制出了一种新型液滴产生器原型:液体被夹在上下两个电极板之间;下极板采用硅作为衬底、LPCVD掺杂多晶硅微电极阵列上热氧化生长的的SiO2薄膜作为介质层;上极板采用ITO透明导电玻璃板作为地电极;另外,在上下极板的表面都均匀旋转涂覆了一层30 nm厚的Teflon薄膜为表面疏水层.实验结果表明,在空气气氛中,该器件在10 Hz 70 V的脉冲电压下成功地实现了从蓄水池中对去离子水滴的分发.     

Physical modeling of hole mobility in silicon inversion layers under uniaxial stress

A physical model for hole mobility under either biaxial or uniaxial stress has been developed. The six-band k ? p theory is used to obtain the bandstructure through stress-dependent Hamiltonian. The hole mobility in the silicon inversion layer is studied in details using Monte Carlo method. A numerically robust method has been applied to achieve self-consistent solution of Poisson’s and Schrödinger equations.     

基于可重构处理器的并行优化算法

为挖掘可重构处理器的内在并行性,需要编译器通过分析程序的并行性来决定可重构处理器硬件最好的执行模式。为此,提出一种基于可重构处理器的并行优化算法。将有向无环图的并行计算部分映射到可重构处理器上,对任务实现3个不同层次的并行性(指令级并行、循环级并行、线程级并行)。测试结果表明,该算法使得可重构处理器在处理任务时比未用并行优化算法的性能提升1.2倍左右。     

接触式智能卡的嵌入式系统攻击平台设计

为了对接触式智能卡的安全性进行研究,搭建了一个多功能的接触式智能卡的嵌入式系统攻击平台,作为开放、可控的目标芯片激励平台;文中给出了具体的实现方案,尤其对智能卡接口电路、读卡器接口电路以及控制模块的设计进行了详细阐述;该平台可以模拟智能卡和读卡器的功能,与真实的智能卡或者读卡器通信,实施中间人攻击、产生侧信道攻击所需的触发信号、向卡片的电源和时钟施加扰动。通过该平台的使用,还可对智能卡芯片安全性设计进行FPGA验证;该方案具有灵活性强、成本低、高效率等优点,可以用于侧信道攻击、故障攻击、密码芯片安全性测试等领域,提高工作效率。     

固体理论进展——半世纪回顾

本文回顾了自1964年密度泛函理论(DFT)提出而引入了被称为第一原理计算电子学近半个世纪以来,固体物理在理论、材料与实验上的进展.所选的关注点是那些和微纳电子学与集成电路技术有关的重大进展.内容分为固体理论与计算电子学、低维与超导材料两个部分.硅基CMOS集成电路在经历了本文涵盖的同一历史时期中令人瞠目的高速发展后,无论在研究与产业上都处于一个新发展阶段的十字路口.通过回顾作为现代信息工程基石的固体器件与理论的进展,可以对今后集成电路的发展趋向提供一个分析参考.     

A Reliable All-2D Materials Artificial Synapse for High Energy-Efficient Neuromorphic Computing

High-performance artificial synaptic devices are indispensable for developing neuromorphic computing systems with high energy efficiency. However, the reliability and variability issues of existing devices such as nonlinear and asymmetric weight update are the major hurdles in their practical applications for energy-efficient neuromorphic computing. Here, a two-terminal floating-gate memory (2TFGM) based artificial synapse built from all-2D van der Waals materials is reported. The 2TFGM synaptic device exhibits excellent linear and symmetric weight update characteristics with high reliability and tunability. In particular, the high linearity and symmetric synaptic weight realized by simple programming with identical pulses can eliminate the additional latency and power consumption caused by the peripheral circuit design and achieve an ultralow energy consumption for the synapses in the neural network implementation. A large number of states up to ≈3000, high switching speed of 40 ns and low energy consumption of 18 fJ for a single pulse have been demonstrated experimentally. A high classification accuracy up to 97.7% (close to the software baseline of 98%) has been achieved in the Modified National Institute of Standards and Technology (MNIST) simulations based on the experimental data. These results demonstrate the potential of all-2D 2TFGM for high-speed and low-power neuromorphic computing.     

Electrically Reconfigurable 3D Spin-Orbitronics

The explosive demands of storage capacity and the von Neumann bottleneck of modern computer architectures trigger many innovations in information technology. Amongst them, nonvolatile spintronics attract considerable attentions for which can embed the computation capability into memory, enable neuromorphic, and probabilistic computing. These exciting progresses typically rely on the manipulation of the relative magnetization orientations of two magnetic layers. By extending to 3D spintronic architectures made of multiple magnetic layers (n), the exponentially increased 2ⁿ magnetic states can provide ample opportunities for implementing novel spintronic functionalities. Here, through building perpendicularly magnetized 3D spin-orbitronic architectures – [Pt/Fe_1−xTb_x/Si₃N₄]_n multilayers, it is demonstrated the electrical programing of 2ⁿ memory states via current-induced spin–orbit torques (SOTs), and the accompanied reconfigurable multifunction in-memory logic features in a single four-terminal Hall device. Further, an electrical readout of these 2ⁿ states, together with the implementation of Boolean logic gates and digital circuitry such as 2–4 and 3–8 decoders, are successfully conducted. More complex logic circuits are also envisioned. The experiments thus substantiate 3D spin-orbitronic structures as a promising platform for exponentially boosting the storage capacity and accommodating in-memory computing that can be important for promoting the emerging 3D nanospintronics.     

面向窄节距倒装互连的预成型底部填充技术

近年来随着电子产品的小型化发展,窄节距倒装芯片互连已经成为研究热点。传统的倒装芯片组装后底部填充技术(例如底部毛细填充)在用于窄节距互连时易产生孔洞,导致可靠性降低,因此产业界开发了面向窄节距倒装芯片互连的预成型底部填充技术,主要包括非流动底部填充和圆片级底部填充。介绍了这类新型底部填充技术的具体工艺及材料需求,并提出了目前其在大规模量产以及未来更窄节距应用中存在的问题及挑战,总结了目前产业界在提高量产生产效率、提升电互连的可靠性以及开发纳米级高热导率填料等方面提出的解决方案,分析了该技术未来的发展方向。